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1/15 ? semiconductor msm51v1000a description the msm51v1000a is a 1,048,576-word 1-bit dynamic ram fabricated in oki's silicon-gate cmos technology. the msm51v1000a achieves high integration, high-speed operation, and low-power consumption because oki manufactures the device in a quadruple-layer polysilicon/single-layer metal cmos process. the msm51v1000a is available in a 26/20-pin plastic soj or 20-pin plastic zip. features ? 1,048,576-word 1-bit configuration ? single 3.3 v power supply, 0.3 v tolerance ? input : lvttl compatible, low input capacitance ? output : lvttl compatible, 3-state ? refresh : 512 cycles/8 ms ? fast page mode, read modify write capability ? cas before ras refresh, hidden refresh, ras -only refresh capability ? package options: 26/20-pin 300 mil plastic soj (soj26/20-p-300-1.27) (product : msm51v1000a-xxjs) 20-pin 400 mil plastic zip (zip20-p-400-1.27) (product : msm51v1000a-xxzs) xx indicates speed rank. product family ? semiconductor msm51v1000a 1,048,576-word 1-bit dynamic ram : fast page mode type msm51v1000a-80 80 ns 150 ns 190 ns 144 mw 126 mw 1.8 mw family access time (max.) cycle time (min.) standby (max.) power dissipation MSM51V1000A-10 t rac 100 ns 45 ns t aa 50 ns 25 ns t cac 30 ns msm51v1000a-70 70 ns 130 ns 162 mw 40 ns 25 ns operating (max.) e2g0056-17-41 this version: jan. 1998 previous version: may 1997
2/15 ? semiconductor msm51v1000a pin configuration (top view) 3 5 7 11 13 15 17 19 d out d in ras a0 a2 v cc a5 a7 1 a9 9 nc 4 6 8 12 14 16 18 20 v ss we nc a1 a3 a4 a6 a8 2 cas 20-pin plastic zip no lead 3 4 5 9 10 11 12 13 ras nc nc a0 a1 a2 a3 v cc 24 23 22 18 17 16 15 14 cas nc a9 a8 a7 a6 a5 a4 2 we 25 d out 1 d in 26 v ss 26/20-pin plastic soj pin name function a0 - a9 address input ras row address strobe cas column address strobe d in data input d out data output we write enable v cc power supply (3.3 v) v ss ground (0 v) nc no connection
3/15 ? semiconductor msm51v1000a block diagram we ras cas timing generator timing generator column decoders write clock generator sense amplifiers i/o selector output buffer d out d in input buffer memory cells row address buffers on chip v bb generator v cc v ss internal address counter column address buffers refresh control clock a0 - a9 row de- coders word drivers 10 10 10 10
4/15 ? semiconductor msm51v1000a electrical characteristics absolute maximum ratings recommended operating conditions capacitance *: ta = 25 c voltage on any pin relative to v ss short circuit output current power dissipation operating temperature storage temperature v t symbol i os p d * t opr t stg C0.5 to 4.6 50 1 0 to 70 C55 to 150 rating ma w c c parameter v unit power supply voltage input high voltage input low voltage v cc symbol v ss v ih v il 3.3 0 typ. parameter 3.0 0 2.0 C0.3 min. 3.6 0 v cc + 0.3 0.8 max. (ta = 0c to 70c) v unit v v v input capacitance (a0 - a9, d in ) input capacitance ( ras , cas , we ) output capacitance (d out ) c in1 symbol c in2 c out 5 5 7 max. pf unit pf pf parameter (v cc = 3.3 v 0.3 v, ta = 25c, f = 1 mhz) typ.
5/15 ? semiconductor msm51v1000a dc characteristics i oh = C2.0 ma output high voltage i ol = 2.0 ma output low voltage 0 v v i v cc + 0.3 v; all other pins not input leakage current under test = 0 v d out disable output leakage current 0 v v o 3.6 v ras , cas cycling, average power t rc = min. supply current (operating) ras , cas = v ih power supply ras , cas current (standby) ras cycling, average power cas = v ih , supply current t rc = min. ( ras -only refresh) ras = v ih , power supply cas = v il , current (standby) d out = enable average power cas before ras supply current ( cas before ras refresh) ras = v il , average power cas cycling, supply current t pc = min. (fast page mode) 3 v cc C0.2 v ras cycling, v oh v ol i li i lo i cc1 i cc2 i cc3 i cc5 i cc6 i cc7 parameter symbol condition msm51v1000 a-70 msm51v1000 a-80 msm51v1000 a-10 min. 2.4 0 C10 C10 max. v cc 0.4 10 10 50 0.5 50 5 50 45 2 min. 2.4 0 C10 C10 max. v cc 0.4 10 10 45 0.5 45 5 45 40 2 min. 2.4 0 C10 C10 max. v cc 0.4 10 10 40 0.5 40 5 40 35 2 unit v v m a m a ma ma ma ma ma ma (v cc = 3.3 v 0.3 v, ta = 0c to 70c) note 1, 2 1, 2 1 1, 2 1, 3 1 notes : 1. i cc max. is specified as i cc for output open condition. 2. the address can be changed once or less while ras = v il . 3. the address can be changed once or less while cas = v ih .
6/15 ? semiconductor msm51v1000a ac characteristics (1/2) random read or write cycle time read modify write cycle time fast page mode cycle time fast page mode read modify write cycle time access time from ras access time from cas access time from column address output low impedance time from cas transition time refresh period ras precharge time ras pulse width (fast page mode) ras hold time cas precharge time (fast page mode) cas pulse width ras pulse width cas hold time cas to ras precharge time ras to cas delay time ras to column address delay time row address set-up time row address hold time column address set-up time column address hold time column address hold time from ras column address to ras lead time access time from cas precharge ras hold time from cas precharge cas to data output buffer turn-off delay time t rc t rwc t pc t prwc t rac t cac t aa t cpa t clz t off t t t ref t rp t ras t rasp t rsh t cp t cas t csh t crp t rcd t rad t asr t rah t asc t cah t ar t ral t rhcp parameter symbol min. 130 160 50 80 0 0 3 50 70 70 25 10 25 70 5 20 15 0 10 0 15 55 35 45 max. 70 25 40 45 20 50 8 10,000 100,000 10,000 45 30 min. 150 180 55 85 0 0 3 60 80 80 25 10 25 80 5 20 15 0 10 0 15 60 40 50 max. 80 25 45 50 20 50 8 10,000 100,000 10,000 55 35 min. 190 220 60 90 0 0 3 80 100 100 30 10 30 100 5 25 20 0 15 0 20 75 50 55 max. 100 30 50 55 20 50 8 10,000 100,000 10,000 70 50 unit ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns note 4, 5, 6 4, 5 4, 6 4 4 7 3 5 6 (v cc = 3.3 v 0.3 v, ta = 0c to 70c) note 1, 2, 3 msm51v1000 a-70 msm51v1000 a-80 msm51v1000 a-10
7/15 ? semiconductor msm51v1000a ac characteristics (2/2) read command set-up time read command hold time read command hold time referenced to ras write command set-up time write command hold time write command hold time from ras write command pulse width write command to ras lead time write command to cas lead time data-in set-up time data-in hold time data-in hold time from ras cas to we delay time column address to we delay time ras to we delay time cas active delay time from ras precharge ras to cas set-up time ( cas before ras ) ras to cas hold time ( cas before ras ) cas precharge we delay time t rcs t rch t rrh t wcs t wch t wp t cwl t rwl t ds t dh t dhr t cwd t awd t rwd t cpwd t rpc t csr t chr t wcr parameter symbol min. 0 0 0 0 15 15 25 25 0 15 55 25 40 70 55 10 10 30 max. unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns note 8 8 9 10 10 9 9 9 9 min. 0 0 0 0 15 15 25 25 0 15 60 25 45 80 60 10 10 30 max. min. 0 0 0 0 20 20 30 30 0 20 75 30 50 100 65 10 10 30 max. 55 ns 60 75 (v cc = 3.3 v 0.3 v, ta = 0c to 70c) note 1, 2, 3 msm51v1000 a-70 msm51v1000 a-80 msm51v1000 a-10
8/15 ? semiconductor msm51v1000a notes: 1. a start-up delay of 100 m s is required after power-up, followed by a minimum of eight initialization cycles ( ras -only refresh or cas before ras refresh) before proper device operation is achieved. 2. the ac characteristics assume t t = 5 ns. 3. v ih (min.) and v il (max.) are reference levels for measuring input timing signals. transition times (t t ) are measured between v ih and v il . 4. this parameter is measured with a load circuit equivalent to 1 ttl load and 100 pf. the output timing reference levels are v oh = 2.0 v and v ol = 0.8 v. 5. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then the access time is controlled by t cac . 6. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then the access time is controlled by t aa . 7. t off (max.) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 8. t rch or t rrh must be satisfied for a read cycle. 9. t wcs , t cwd , t rwd , t awd and t cpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. if t cwd 3 t cwd (min.) , t rwd 3 t rwd (min.), t awd 3 t awd (min.) and t cpwd 3 t cpwd (min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. these parameters are referenced to the cas leading edge in an early write cycle, and to the we leading edge in a read modify write cycle.
9/15 ? semiconductor msm51v1000a ras cas address we d out v ih v il C C v ih v il e e v ih v il e e v ih v il e e v oh v ol e e t rc t ras t rp t csh t crp t rcd t rsh t crp t cas t rad t ral t asr t rah t asc t cah row column t ar t rcs t rch t rrh t cac t aa t clz t rac t off open valid data "h" or "l" timing waveform read cycle write cycle (early write) ras cas address we d out v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C "h" or "l" d in v ih v il e e t rc t ras t rp t csh t crp t rcd t rsh t crp t cas t ar t rad t ral t rah t asr t asc t cah row column t cwl t wcr t wcs t wch t rwl t dhr t ds t dh valid data open t wp e2g0088-17-41a
10/15 ? semiconductor msm51v1000a read modify write cycle fast page mode read cycle ras cas address we d out v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C "h" or "l" t rasp t rp t csh t crp t rcd t cas t cp t pc t cas t cp t rsh t cas t crp t ar t asr t rah t asc t cah t asc t cah t ral t asc t cah row column column column t rad t rcs t rch t rcs t rch t rcs t rrh t rch t cac t aa t rac t cac t aa t cpa t cac t aa t cpa valid data valid data valid data t clz t off t clz t off t clz t off t rhcp ras cas address we d out v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C "h" or "l" d in v ih v il e e t rwc t rp t ras t crp t rcd t rsh t rwl t cas t crp t csh t ar t cwl t rad t ral t asr t rah t asc t cah row column t awd t rwd t cwd t wp t rcs t ds t dh valid data t cac t aa t rac open t off valid data t clz
11/15 ? semiconductor msm51v1000a fast page mode write cycle (early write) fast page mode read modify write cycle ras cas address we d out v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C "h" or "l" d in v ih v il e e t rasp t rp t crp t rcd t cas t cp t pc t cas t cp t cas t rsh t crp t ar t asr t rah t asc t cah t asc t cah t asc t cah t ral row column column column t rad t wcr t wcs t wch t wcs t wch t wcs t wch t ds t dh t ds t dh t ds t dh valid data valid data valid data open t dhr t rhcp t wp t cwl t wp t wp t cwl t cwl t rwl ras cas address we d out v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C "h" or "l" d in v ih v il e e t rasp t csh t prwc t rcd t cas t cp t cas t rsh t rp t crp t cas t ar t asr t rah t asc t cah t asc t cah t asc t cah t ral row column column column t rwd t rcs t cwd t cwl t cwd t cwl t cwd t cwl t awd t aa t rad t cac t wp t awd t cpa t aa t cac t off t wp t awd t cpa t aa t cac t off t wp t off valid data valid data valid data t rac t clz t ds t dh t clz t ds t dh t clz t ds t dh t rwl valid data valid data valid data t cp t rcs t rcs t rhcp t cpwd t cpwd
12/15 ? semiconductor msm51v1000a ras -only refresh cycle cas before ras refresh cycle ras cas address d out v ih v il C C v ih v il C C v ih v il C C v oh v ol C C "h" or "l" t rc t rp t ras t rpc t crp t rah t asr row open note: we = "h" or "l" t off ras cas d out v ih v il C C v ih v il C C v oh v ol C C t rc t ras t rp t rpc t cp t csr t chr t off open note: we , address = "h" or "l"
13/15 ? semiconductor msm51v1000a hidden refresh read cycle ras cas address we d out v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C "h" or "l" t rc t ras t rp t ras t crp t rcd t rsh t chr t rad t ral t asr t rah t asc t cah t ar t rcs t rrh t cac t aa t rac t off t clz valid data row column hidden refresh write cycle ras cas address we d out v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C "h" or "l" d in v ih v il e e t rc t ras t rp t ras t crp t rcd t rsh t chr t ar t rad t ral t asr t rah t asc t cah row column t rwl t wcr t wcs t wch t ds t dh valid data open t dhr t rad t wp
14/15 ? semiconductor msm51v1000a (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). soj26/20-p-300-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.80 typ. mirror finish
15/15 ? semiconductor msm51v1000a (unit : mm) zip20-p-400-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.50 typ. mirror finish

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